B.Sc. 4th Semester Physics Project file लेबलों वाले संदेश दिखाए जा रहे हैं. सभी संदेश दिखाएं
B.Sc. 4th Semester Physics Project file लेबलों वाले संदेश दिखाए जा रहे हैं. सभी संदेश दिखाएं

सोमवार, 15 जून 2026

Experiment No . 1 ( B.Sc. 4th Semester Physics Project file )

 

Experiment No. 5  bsc.3rd semester

To study the Wien bridge oscillator and visualize effect on output frequency with variation in R and C . 
Object

            To study and verify the truth table g basic logic gates (NOR, AND, OR)

Apparatus Required

Prototyping board (Bread board) DC power supply connecting wires .

Theory  

            AND, OR and NOT are basic logic gates in electronic circuits because they are made up and no .and electronic devices. in pats and out puts & logic gates can occur only in two levels . These two levels are tern High and Low or truth and false or ON and OFF or simply 1 and o .we use ally express values into truth table. Logic gates are mainly based on Boolean   funcation .

NOT  GATE

            A NOT gate is also known as inverter has only one input and only one output It is a device whose output is always the complement & its input when the input is 1 (one) the output is o and vice – versa .

With input variable A, the Boolean expression for output can be written as .

                                    Y = Ᾱ

AND GATE

            An AND gate has two  or more inputs but only one output when all the inputs are 1 the output I there gate is 1 AND gate is also called an all or nothing gate with input variables A and B the Boolean expression for output is .

                                    Y = A . B

OR Gate

            OR gate may have two or two or more inputs but only one output if at least one I the input is 1 the output will be 1 With input variables ‘A’ and ‘B’ the Boolean expression for output is

                                    Y = A + B

Observation

1.      Truth table for NOT Gate .

Input

Output

A

Y = Ᾱ

0

1

1

0

 

2.      Truth table for AND gate

Input

 

Output

A

B

Y = A . B

0

0

0

0

1

0

1

0

0

1

1

1

 

3.      Truth table for OR Gate.

                                    Input

 

Output

A

B

Y = A .B

0

0

0

0

1

1

1

0

1

1

1

1

           

Result

            Truth table for NOT , AND , OR gate are  & tained .

Precautions

1.      All the contacts should be tight enough

2.      Since the components applied in the circuit are semi – conductor materials the applied voltage should not be high.

Experiment  No . 1 .4semester

Object

            To study the we in bridge oscillator and visualize effect on output frequency with variation in RC combination .

Apparatus Used

            2 mm patch card , oscilloscope .

Formula Used

                                    .f = 1/2π . √R₁.√R₂.√c₁.√c₂

                        If          R₁ = R₂ = R

                        &         C₁ = C₂ = C

                        Then ,  f = 1/2π . √RC

Observation table

S . No

Resistance value

Theoretical value of resource frequency

Practical value of resource frequencies

1.

R₄ = R₈ = 10K

1.592

1.635

2.

R₅ = R₉ = 20K

0.796

0.820

3.

R₆ = R₁ₒ = 39K

0.408

0.419

4.

R₇ = R₁₁ = 100K

0.159

0.164



Result

            Theoretical value of resonance frequency = 0.738

Experimental value of resonance frequency = 0.759

Precautions

1.      Make the connection carefully .

Adjust the potentiometer of CRD & ware seen on CRO with carefully.

Note.

(Please note: if a particular experiment is not visible, please search for it using the search box—for example, Experiment No. 2. (To study the transistor bias stability.)

कृपया ध्यान दीजिये अगला  एक्सपेरिमेंट दिख रहा हो वो आप सर्च बॉक्स में सर्च कर लीजिये . जैसे , एक्साप्रिमेंट नंबर.2 या फिर  (To study the transistor bias stability.)




Experiment No . 2 ( B.Sc. 4th Semester Physics Project file )

Experiment No. 2  bsc.4th semester

To study the transistor Bias stability.

Object

            To study the transistor Bias stability .

Apparatus

Connecting wire, power supply , pencil etc .

Formula Used

                        Voltage gain = Volt/Vin

Observation Table            Vᴄc = 12V , Vin = 1V

S . No.

RE ()

Vin

A (Voltage gain)

Output

1.

0

0.45

1.45

3.80

2.

50

0.45

11.35

4.92

3.

100

0.45

9.05

3.90

4.

150

0.45

7.02

2.78

5.

200

0.45

5.91

2.13

6.

250

0.45

3.94

1.40

7.

300

0.45

3.38

0.82

 

Observation Table

                                    For Vᴄᴄ = 6V , Vin = 1V

S . No

RE ()

Vin

A (Voltage gain)

Output

1.

0

0.45

7.28

2.60

2.

50

0.45

5.95

2.12

3.

100

0.45

5.91

2.09

4.

150

0.45

5.75

2.09

5.

200

0.45

5.27

1.85

6.

250

0.45

3.65

1.80

7.

300

0.45

2.20

0.5

 Result

            The diagram characteristic transistor and biasing is studied.

Precautions

1.      Graph should be clear.

2.      Take reading carefully.

3.      Connection should be tight. 

Note.

(Please note: if a particular experiment is not visible, please search for it using the search box—for example, Experiment No. 3. (To draw the characteristic of a PNP junction transistor in common emitter arrangement.)

कृपया ध्यान दीजिये अगला  एक्सपेरिमेंट दिख रहा हो वो आप सर्च बॉक्स में सर्च कर लीजिये . जैसे , एक्साप्रिमेंट नंबर.3 या फिर  (To draw the characteristic of a PNP junction transistor in common emitter arrangement.)

Experiment No . 3 ( B.Sc. 5th Semester Physics Project file )

Experiment No. 3 bsc.5 th semester To determine the refractive index of the material of a prism using sodium light. Object             ...